Power semiconductor devices, like power MOSFETs, or power diodes, are widely used in high power applications. Power devices, depending on their specific design, can have a voltage blocking capability ranging from several ten volts to several hundred volts or even some kilovolts. One challenge in the design of power semiconductor device is to provide a low on-resistance at a given blocking voltage capability.
Power semiconductor devices include a pn-junction that is formed between a p-doped semiconductor region and an n-doped semiconductor region. The component blocks when the pn-junction is reverse-biased. In this case a depletion region or space charge region propagates in the p-doped and n-doped regions. Usually one of these semiconductor regions is more lightly doped than the other one of these semiconductor regions, so that the depletion region mainly extends in the more lightly doped region, which mainly supports the voltage applied across the pn-junction. The semiconductor region supporting the blocking voltage is referred to as drift region in an MOSFET, and is referred to as base region in a diode.
Superjunction or compensation components additionally to a drift or base region include compensation regions which are doped complementarily to the drift region and which are arranged adjacent to the drift regions. When a blocking voltage is applied to the pn-junction of such component and a depletion region propagates in the drift region, dopant charges present in the drift region and dopant charges present in the compensation regions compensate one another. Thus, in order to obtain a given voltage blocking capability, the drift region in a superjunction device can be more highly doped than the drift region in a conventional device, which results in a lower on-resistance.
Drift regions and compensation regions of a superjunction device are, for example, formed by epitaxially growing a plurality of semiconductor layers one above the other. In these epitaxially grown semiconductor layers n-type dopant regions and p-type dopant region are formed such that within the individual semiconductor layers n-type dopant regions and p-type dopant regions are arranged alternatingly, and such that in the arrangement with the plurality of semiconductor layers p-type dopant regions are arranged one above the other and n-type dopant regions are arranged one above the other. Dopants of the p-type dopant regions and n-type dopant regions are then diffused into surrounding semiconductor regions by heating-up the semiconductor body to a desired diffusion temperature. Dopants that diffuse from n-type dopant regions arranged one above the other form an n-doped column extending in a vertical direction of the semiconductor layer arrangement, and dopants from the p-type dopant regions form a p-doped column in the semiconductor layer arrangement. These n-doped and p-doped columns form drift and compensation regions in the completed device.
One further challenge in the design of power semiconductor devices is to shrink the devices, i.e. is to reduce their size, without reducing their current bearing capability and their voltage blocking capability. Shrinking a superjunction device requires reducing the size of the n-doped and p-doped columns in a direction which is a direction perpendicular to the current flow direction in the device. In the diffusion process explained hereinabove the n-type dopants and the p-type dopants do not only diffuse in the vertical direction of the semiconductor layer arrangement, but also diffuse in the horizontal direction. Due to this diffusion in the horizontal direction the size of the n-doped and p-doped columns cannot be reduced arbitrarily.
According to a further known method, a plurality of semiconductor layers is epitaxially grown one above the other on a semiconductor substrate, wherein in each of these semiconductor layers n-type dopant regions and p-type dopant regions are produced to be arranged alternatingly within the individual semiconductor layers and one above the other in a vertical direction of the semiconductor layer arrangement. In this semiconductor layer arrangement trenches are formed between the n-type dopant regions and the p-type dopant regions, and these trenches are filled with a filling material, like a dielectric material. These trenches filled with the isolation material limit the diffusion of n-type dopant and p-type dopant in the horizontal direction, so that narrow n-doped and p-doped columns can be formed.
This method, however requires that deep trenches are formed which extend through the plurality of epitaxially grown semiconductor layers. Trenches in semiconductor material cannot be produced to be perfectly vertical, i.e. such trenches are usually inclined relative to the vertical direction. This has the effect that an opening at the top of a trench is offset relative to the bottom of the trench. With a trench depth of, for example, 50 μm an angle of 0.5° already results in an offset of several 100 nm. The smallest possible dimension of an n-doped column or a p-doped column is given by the smallest possible distance between two trenches. Due to the inclination of deep trenches and the offset resulting therefrom, the distance between two trenches and, therefore, the dimension of the n-doped and p-doped columns cannot be reduced arbitrarily.
There is, therefore, a need for providing semiconductor devices with narrow n-doped and p-doped columns arranged next to each other in a semiconductor body.